Extraction and Modeling of Process Variations for Robust Nanoscale Design

Statistical analysis and optimization is critical for robust nanoscale circuit design. To accurately perform such analysis, primary process variation sources must be identified and their distributions must be well characterized. We present a rigorous method to extract process variations from in-situ IV measurements. Transistor statistics are collected from a test chip fabricated in a 65nm SOI process. We decompose the variations of gate length (L), threshold voltage (Vth) and other three parameters primarily from the leakage and linear current. Both L and Vth variations are normally distributed, with negligible spatial correlation. By including variations in the model file, we can accurately predict drive current in all process corners. The new extraction method supports statistical design with sufficient model fidelity.